(1) Field of the Invention
The invention relates to processes for the manufacture of integrated circuits and more particularly to the area of forming three-dimensional integrated circuits by wafer stacking.
(2) Background of the Invention and Description of Previous Art
In the apparent never ending quest towards further miniaturization and increasing circuit density of solid state integrated circuits, the technology has been forced to develop new packaging approaches, other than discrete single surface silicon chips. One such approach involves packaging integrated circuits using multiple chips layered and interconnected one upon the other. Although the concept of multilayered chips is old, the technology to produce them cost effectively was not available. Such processes as SOI (Silicon On Insulator) and SOS (Silicon On Sapphire) as well a the bonding of discrete devices, such as MEMS (Micro-Electro-Mechanical-Systems) onto integrated circuit chips were well known but not cost or design effective. In recent years however, with the development of high precision wafer thinning methods such as CMP (Chemical Mechanical Polishing) and DRIE (Deep Reactive Ion Etching) in conjunction with improved bonding methods and materials such as fine adhesives, multiple chip stacking has become increasingly desirable as well as practical. In addition, these improvements have also allowed the formation of items, which were previously impossible because of processing incompatibilities. Wada, et al, U.S. Pat. No. 6,666,943, describes a process of transferring a film which has been annealed at a high temperature on a first substrate, onto a second substrate which could not have endured such an anneal if the film were deposited directly on it. The process is only capable of transferring deposited films from one substrate to another and the separation requires a lift-off process.
Yang, et al, U.S. Patent Application number 2002/0106867 A1 describes a method for transferring a membrane from one wafer to another wafer to form integrated semiconductor devices wherein a carrier wafer is fabricated with a membrane on one surface. The membrane is then bonded to a device wafer by a plurality of joints. The joints and the device wafer are then isolated from exposure to etching chemicals and the carrier wafer is then selectively etched away from the back to expose the membrane and leave the membrane bonded to the device wafer. The method requires special tools to transfer the layers. RIE using a shadow mask, as applied by the reference to selectively remove peripheral portions of the carrier wafer, poses critical alignment problems. Further, the method is not suitable for wafer level post processing. In Yang, et al. U.S. Patent Application number 2004/0063322 A1, wet etching to remove the carrier wafer is replaced by gaseous etching and the surfaces of the device wafer are protected by an oxide layer.
Niklaus, et al. “Low Temperature Wafer-Level Transfer Bonding”, Journal of Microelectromechanical Systems. Volume 10, No. 4, December 2001, pages 525-531 shows that by bonding a target wafer onto a base wafer by means of a BCB (benzocyclobutene) bonding process, it is possible to thin down the target wafer to a desired thickness by a grinding/etching process to reach an etch-stop layer. Dekker, et al. “Substrate Transfer: Enabling Technology for RF Applications”, IEDM 2003, similarly shows that, by bonding a CMOS device wafer on SOI onto a glass substrate by means of a polymer glue layer and thinning, it is possible to achieve high Q RF systems. None of these approaches, however, are suitable for thicker substrate transfer for MEMS or Wafer level packaging applications.
Zavracky, et al, U.S. Pat. No. 5,793,115 cites a method of integrating a three dimensional processor using transferred thin film circuits. It describes specifically, how a microprocessor may be configured with different layers and interconnected vertically through insulating layers, which separate each circuit layer of the structure. Each circuit layer can be fabricated on a separate wafer or thin film material and then transferred onto the layered structure and interconnected. The reference only describes a 3D-system design or architecture and does not relate how the 3D-wafer stack is formed. Colinge, et al. “Silicon Layer Transfer Using Wafer Bonding and Debonding”, Journal of Electronic Materials, Volume 30, No. 7, 2001, pages 841-844 describes a method of separating and transferring thin silicon layers from a base wafer by a hydrogen implanted Ion-cut method.
Sterrett, U.S. Pat. No. 6,586,843 B2 cites a method for bonding and interconnecting a flip-chip die onto a substrate using a partially cured BCB as a bonding adhesive and as a connection bump. Finnila, U.S. Pat. No. 5,426,072 cites a process for manufacturing a three dimensional integrated circuit using stacked thin silicon layers formed from SOI substrate wafers. Integrated circuits are first formed on the thin silicon layer of an SOI wafer. Indium bumps are formed on the upper surface of the integrated circuit and conductive feed-throughs are formed extending to the subjacent sacrificial oxide layer. A carrier wafer is then bonded on top of the passivated integrated circuit and the SOI substrate and sacrificial oxide are removed. Metallization and indium bumps are then formed on the now exposed bottom of the thin silicon layer, connecting to the feed-throughs. The thin silicon layer is then bonded, either to a final base substrate or to a previously formed thin silicon layer. The carrier wafer is then removed. Additional thin silicon layers may be formed on other SOI wafers, prepared in a similar way, and successively bonded to the first thin silicon layer to form a stack. The method requires bumps and UBM (Under Bump Metallization) at each layer, which adds to the process complexity as well as cost. In addition, through wafer metallization is formed in two stages, both prior to final bonding to the permanent substrate, thereby requiring additional processing steps.
Tsai, et al., U.S. Pat. No. 6,319,831 cites a two-stage method of ECD which includes a first low current density plating stage wherein the copper deposition is slow but highly conformal. In the second, high current density stage, the brighteners and levelers in the plating bath are depleted which enhances the growth rate of copper at the base of the opening, thereby inhibiting void formation.